This invention relates to a circuit arrangement comprising a plurality of sub-circuits for data processing, the sub-circuits being provided with clock inputs for receiving clock signals for synchronizing the operation of the sub-circuits. In particular, the invention relates to a circuit arrangement comprising semiconductor integrated circuits for data processing wherein the operation of the sub-circuits in the system has to be synchronized for proper operation. In the context of the present description with, by data processing is meant the handling of any type of data independent of the associated information content or the way the information is represented.
Such a circuit arrangement is known from EP-A 0 133 359. That document describes a microprocessor chipset in which each chip receives clock pulses from a system clock and is synchronized by an associated controller. The chips are provided with adjustable delay circuits to adjust the timing of the clock pulses. Adjustment of the delay circuits occurs in response to a system clock pulse and to an internal clock pulse from the chip. For each chip or sub-circuit such a separate synchronizer is necessary to adjust the clock signals to the speed of the flow of the data signals through the circuit arrangement.
The known circuit arrangement has several drawbacks. When implemented in a digital circuit, the controller circuits must be faster than any data processing circuitry clocked by the clock pulses. Consequently, the maximum possible speed of the data processing circuitry is below the speed achievable with the available technology. The use of analog circuitry in the controller, to enhance speed, makes it impossible to integrate the circuit on a semiconductor chip in, for example, CMOS technology without a loss of performance of the overall circuit.
Another very serious disadvantage of the use of synchronizers in a data processing system is that errors are possible in the synchronizers while transferring clock pulses from the central clock to the individual sub-circuits. As is shown by H. J. M. Veendrick in the article "The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate", in IEEE Journal of solid-state circuits, Vol SC-15, No. 2, April 1980, pp 169-176, there is a chance that a metastable state occurs in the synchroniser, for example, when the temperature of the circuit changes. This causes an imperfect phase relationship whereby data pulses are lost or duplicated. The failure rate increases greatly with the signal frequency.